1. Field of the Invention
The present invention relates to a read device and a read method for a semiconductor memory, particularly to a read device for a semiconductor memory which reads out stored data by boosting an internal power supply voltage.
2. Description of the Related Art
Conventionally, there have been semiconductor memories in which data stored in a memory cell is read out by comparing the output voltage of the memory cell storing the data with the output voltage of a reference cell. Such semiconductor memories include non-volatile semiconductor memories in which data is stored by utilizing the difference in threshold voltage between the memory cell and the reference cell.
For example, in a stacked-gate type non-volatile semiconductor memory such as a flash memory, data is stored in a memory cell by utilizing the phenomenon that the threshold voltage varies in accordance with the number of electrons existing in the floating gate of the transistor making up the memory cell. In case of a memory cell that stores binary data, the threshold voltage of the memory cell is set to fall within one of two threshold voltage ranges.
When reading out data stored in a memory cell as described above, first, the cell current of the memory cell and that of a reference cell, which can be obtained by a read operation, are converted to voltage level signals, respectively. By comparing the voltage level signals with each other, which have been obtained as a result of the conversion, the data stored in the memory cell is read out.
FIG. 1 is a representation for illustrating a relationship among output levels (threshold voltages) of memory cells and those of reference cells in a prior art. FIG. 1 shows the relationship among the output levels (threshold voltages) in the memory cells storing binary data.
In FIG. 1, the threshold voltage (VTH1) of a memory cell storing data xe2x80x981xe2x80x99 is set to be lower than the threshold voltage (VTHe) of an erase verify reference cell which is a first threshold voltage. The threshold voltage (VTH0) of a memory cell storing data xe2x80x980xe2x80x99 is set to be higher than the threshold voltage (VTHw) of a write verify reference cell which is a second threshold voltage.
The first threshold voltage (VTHe) is set to be lower than the second threshold voltage (VTHw), and the threshold voltage (VThr) of a read reference cell is set to be between the first threshold voltage (VTHe) and the second threshold voltage (VTHw) . In other words, the threshold voltages are set to satisfy the relationship of VTH0 greater than VTHw greater than VTHr greater than VTHe greater than VTH1.
In recent years, along with the widespread use of portable information devices, a low voltage operation has been required in a non-volatile semiconductor memory. When performing a low voltage operation in a non-volatile semiconductor memory, the voltage of a word line was generally boosted so as to increase the difference between the cell current of a memory cell and that of a reference cell in the read operation, thereby reading out data stored in the memory cell. Moreover, in a non-volatile semiconductor memory, a series of read operations, including the timing to boost the voltage of the word line, etc., were controlled by a timing circuit provided in a non-volatile semiconductor memory in order to reduce the stand-by current.
FIG. 2 is a diagram illustrating an exemplary configuration of a conventional read device for a flash memory using a timing circuit.
In FIG. 2, reference numeral 601 denotes an address buffer. The address buffer 601 converts an externally input address to an internal address to be used in the flash memory and outputs the internal address. Reference numeral 602 denotes an address transition detection circuit. The address transition detection circuit 602 detects a change in the internal address supplied from the address buffer 601.
If a change in the internal address is detected, the address transition detection circuit 602 outputs an address transition signal ATD, and notifies the change in the internal address to a timing circuit 612 and a word line boost circuit 603.
The word line boost circuit 603 generates a voltage VWL for boosting one of word lines WL0, WL1, . . . , WLn which is selected by a row decoder 604 on the basis of the address transition signal ATD supplied from the address transition detection circuit 602. The row decoder 604 selects and activates one of the word lines WL0, WL1, . . . , WLn of a memory cell array 606 according to the internal address supplied from the address buffer 601.
Reference numeral 605 denotes a column decoder. The column decoder 605 selects and activates one of bit lines BL0, BL1, . . . , BLn of the memory cell array 606 according to the internal address supplied from the address buffer 601. Consequently, the desired memory cell in the memory cell array 606 is selected, and the cell current indicating the stored data is supplied to a first cascade type sense circuit 607. The first cascade type sense circuit 607 converts the cell current of the memory cell supplied from the column decoder 605 to a voltage level signal SAI, and outputs the signal to a sense amplifier 608.
Reference numeral 609 denotes a reference word line driver. The reference word line driver 609 activates a word line for reading a reference cell 610, based on which it is determined whether the data stored in the memory cell is xe2x80x980xe2x80x99 or xe2x80x981xe2x80x99. Consequently, the cell current of the reference cell 610 is supplied to a second cascade type sense circuit 611. In order to read the reference cell 610 under the same conditions as those with the memory cell, a voltage VWL for boosting the voltage of a word line is supplied to the reference word line driver 609 from the word line boost circuit 603. The second cascade type sense circuit 611 converts the cell current of the reference cell supplied from the reference cell 610 to a voltage level signal SAREF, and outputs the signal to the sense amplifier 608.
The sense amplifier 608 compares the voltage value of the signal SAI supplied from the first cascade type sense circuit 607 with that of the signal SAREF supplied from the second cascade type sense circuit 611. In accordance with the comparison result, the sense amplifier 608 determines whether the data stored in the memory cell is xe2x80x980xe2x80x99 or xe2x80x981xe2x80x99.
More specifically, if the voltage value of the signal SAI supplied from the first cascade type sense circuit 607 is higher than that of the signal SAREF supplied from the second cascade type sense circuit 611 by a predetermined voltage or more, the data stored in the memory cell is determined to be xe2x80x980xe2x80x99. On the other hand, if the voltage value of the signal SAI supplied from the first cascade type sense circuit 607 is lower than that of the signal SAREF supplied from the second cascade type sense circuit 611 by an a predetermined voltage or more, the data stored in the memory cell is determined to be xe2x80x981xe2x80x99.
A timing circuit 612 controls respective operation timings of the circuits in the read operation, e.g., the timing at which the voltage of a word line is boosted, the timing at which data is latched, etc., based on the address transition signal ATD supplied from the address transition detection circuit 602.
Reference numeral 613 denotes a latch circuit.
The latch circuit 613 receives the data stored in the memory cell, which has been determined by the sense amplifier 608, in response to a latch signal LT supplied from the timing circuit 612, and temporarily stores the data. The latch circuit 613 supplies the received data to an output buffer 614. The output buffer 614 is a transistor buffer having a high output ability, and outputs the data stored in the memory cell, which has been supplied from the latch circuit 613, to the outside.
FIG. 3 is a diagram illustrating a circuit configuration of the first cascade type sense circuit 607 illustrated in FIG. 2. The first cascade type sense circuit 607 comprises a load 701 such as a resistor, a transistor 702, and an inverter 703. A power supply, the load 701, the transistor 702, the output node of the column decoder 605 are serially 6connected with one another in this order. A signal line of the signal SAI is connected to the intermediate node between the load 701 and the transistor 702. The output of the transistor 702 is fed back to the transistor 702 via the inverter 703.
The first cascade type sense circuit 607 constantly maintains the output voltage of the transistor 702 at a predetermined voltage, thereby converting the supplied cell current to the voltage level signal SAI. For example, assume a case where the threshold voltage of the memory cell storing the data xe2x80x981xe2x80x99 is lower than 4V, and the threshold voltage of the memory cell storing the data xe2x80x980xe2x80x99 is higher than 4V. While maintaining the output voltage of the transistor at 1V, the gate voltage of 4V is supplied to the memory cell, and the data stored in the memory cell is read out.
If the data stored in the memory cell is xe2x80x981xe2x80x99, the supplied gate voltage is higher than the threshold voltage. Thus, a cell current flows through the memory cell, and the voltage value of the signal SAI is thereby reduced. If the data stored in the memory cell is xe2x80x980xe2x80x99, the supplied gate voltage is lower than the threshold voltage. Therefore, no cell current flows through the memory cell, and the voltage value of the signal SAI maintains a high value.
FIG. 4 is a timing chart for illustrating the read operation of the read device for the flash memory illustrated in FIG. 2.
In FIG. 4, an address is supplied from the outside to the address buffer 601 at a time t10. The address buffer 601 converts the supplied address to an internal address to be used in the flash memory, and supplies the address to the address transition detection circuit 602. The address transition detection circuit 602 detects a difference of the internal address supplied from the address buffer 601, from the internal address which has been supplied prior to the time t10, and activates the address transition signal ATD. By activating the address transition signal ATD, the word line boost circuit 603 starts a boost operation. Thereafter, the voltage VWL continues to be raised. Also, the timing circuit 612 starts an operation timing control for each of the circuits in the read operation.
The internal address converted by the address buffer 601 is supplied to the row decoder 604 and the column decoder 605. According to the supplied internal address, the row decoder 604 and the column decoder 605 select and activate one of the word lines and one of the bit lines in the memory cell array 606, respectively. Consequently, the cell current indicating the data stored in the desired memory cell is supplied to the first cascade type sense circuit 607 from the column decoder 605. The cell current is converted to the voltage level signal SAI at the first cascade type sense circuit 607, and the converted signal is supplied to the sense amplifier 608.
Concurrently, the reference cell 610 is also read. The second cascade type sense circuit 611 converts the cell current to the voltage level signal SAREF, and the converted signal is supplied to the sense amplifier 608.
During this, the voltage VWL is boosted by the word line boost circuit 603, and the voltage values of the signals SAI and SAREF which are supplied to the sense amplifier 608 respectively from the first cascade type sense circuit 607 and the second cascade type sense circuit 611 are gradually increased as illustrated in FIG. 4.
At a time t11, after the elapse of a comparison preparation period from the time t10, the timing circuit 612 activates the latch signal LT for receiving the data stored in the memory cell, and supplies it to the latch circuit 613. Herein, the comparison preparation period refers to a period which is preset so that a correct read-out result can be obtained. The comparison preparation period is set in consideration of the rising time of a word line, and the period of time necessary for the voltage values of the signals SAI and SAREF to reach voltage values which can be compared with each other by the sense amplifier 608.
The latch circuit 613, which has received the activated latch signal LT, latches the data stored in the memory cell which has be en supplied from the sense amplifier 608. Consequently, at a time t12, the data stored in the memory cell corresponding to the externally input address is output from the output buffer 614. A period of time from the time t10 to the time t12 is referred to as a read operation period.
In the conventional read device as described above, the read operation period (the period of time from the time the to the time t12) is a fixed period of time. More specifically, a period of time from the start of the read operation to a point in time when the latch signal LT is activated (the data stored in the memory cell supplied from the sense amplifier 608 is latched in the latch circuit 613) is a certain period of time.
However, when data stored in memory cells is sequentially read out and output, data to be output changes in a short cycle (period of time), for example, in case of the read operation in a page mode or in a burst mode, thereby resulting in a reduction in the internal power supply voltage. Along with the reduction in the internal power supply voltage, a difference between the voltage values of the signals SAI and SAREF is reduced accordingly, and thus, it requires a long time before these voltage values can be compared with each other by the sense amplifier 608. Particularly in a non-volatile semiconductor memory which operates at a low voltage, since the read operation is performed by boosting the internal power supply voltage, it requires a long time before the voltage values can be compared with each other by the sense amplifier 608.
Therefore, when data stored in memory cells is sequentially read out and output, the latch signal LT may be activated before the voltage values can be compared with each other by the sense amplifier 608. In other words, when the sense amplifier 608 is outputting false data, the latch signal LT is activated, thereby outputting the false data to the outside.
It is an object of the present invention to provide a read device and a read method for a semiconductor memory, wherein data stored in a memory cell can be properly output to the outside even when a reduction of an internal power supply voltage occurs.
The present invention is directed to a read device for a semiconductor memory that comprises a memory cell and a first reference cell for outputting a voltage at a first reference level to be compared with the output voltage of the memory cell. The device reads out the stored data of the memory cell by comparing the output voltage of the memory cell with the output voltage of the first reference cell. The device comprises a judging section for judging as to whether or not the output voltages of the memory cell and the first reference cell have reached their respective comparable levels; and a comparing section for comparing the output voltage of the memory cell with the output voltage of the first reference cell in accordance with the result of judgment by the judging section, and outputting the comparison result as the stored data of the memory cell.
According to another aspect of the present invention, the memory further comprises a second reference cell for outputting a voltage at a second reference level higher than the first reference level; and a third reference cell for outputting a voltage at a third reference level lower than the first reference level, and the judging section compares the output voltage of the first reference cell with the output voltage of the second reference cell and with the output voltage of the third reference cell, for judging, on the basis of the comparison results, as to whether or not the output voltages of the memory cell and the first reference cell have reached their respective comparable levels.
The present invention is also directed to a read method for a semiconductor memory that comprises a memory cell and a first reference cell for outputting a voltage at a first reference level to be compared with the output voltage of the memory cell. The stored data of the memory cell is read out by comparing the output voltage of the memory cell with the output voltage of the first reference cell. The method comprises the steps of judging as to whether or not the output voltages of the memory cell and the first reference cell have reached their respective comparable levels; comparing the output voltage of the memory cell with the output voltage of the first reference cell in accordance with the judgment result; and outputting the comparison result as the stored data of said memory cell.
According to another aspect of the present invention, the memory further comprises a second reference cell for outputting a voltage at a second reference level higher than the first reference level; and a third reference cell for outputting a voltage at a third reference level lower than the first reference level, and the output voltage of the first reference cell is compared with the output voltage of the second reference cell and with the output voltage of the third reference cell, for judging, on the basis of the comparison results, as to whether or not the output voltages of the memory cell and the first reference cell have reached their respective comparable levels.
According to the present invention, it is judged whether or not the output voltage of a memory cell and the output voltage of a first reference cell have reached their respective comparable levels. In accordance with the judgment result, the comparison result between the output voltage of the memory cell and the output voltage of the first reference cell is output as data stored in the memory cell. Accordingly, even when a reduction of the internal power supply voltage occurs, it is possible to output properly the comparison result as the data stored in the memory cell always after the output voltage of the memory cell and the output voltage of the first reference cell have reached their respective comparable levels.
In the case where it is judged whether or not the output voltage of a memory cell and the output voltage of the first reference cell have reached their respective comparable levels, by comparing the output voltage of the first reference cell with the output voltage of the second reference cell, and by comparing the output voltage of the first reference cell with the output voltage of a third reference cell, it is possible to output properly the comparison result as data stored in the memory cell always after the output voltage of the memory cell and the output voltage of the first reference cell have reached their respective comparable levels, for both the voltages higher and lower than the voltage at the first reference level, even when a reduction of the internal power supply voltage occurs.